Huawei has unveiled the Tau (τ) Scaling Law and a new LogicFolding chip architecture, aiming to build 1.4nm-class chips by 2031 without ASML's EUV lithography machines. Announced by chip chief He Tingbo at IEEE ISCAS 2026 in Shanghai, the design stacks logic circuits to boost transistor density by 55% and power efficiency by 41%. The tech debuts in Huawei's Kirin processor for the Mate 90 series this autumn, challenging Moore's Law and US sanctions.